An Interpolated Flying-Adder-Based Frequency Synthesizer

This work presents an interpolated flying-adder(FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle jitter and root-mean-square (RMS) jitter performance. A multiphase all-digital phase-locked loop (ADPLL) provides steady reference signals for the interpolated flying adder. This paper reveals implementation skills of a multiphase ADPLL, as well as an interpolated flying adder. In addition, analytical details of the jitter performance are derived. A test chip for the proposed interpolated FA-based frequency synthesizer was fabricated in a standard 0.18 μm CMOS technology, and the core area was 0.143mm2. The output frequency had a range of 33MHz ∼ 286MHz at 1.8 V with peak-to-peak (Pk-Pk) jitter 215.2 ps at 286MHz/1.8 V.